1. Field
This invention relates generally to integrated circuits and more particularly to reconfigurable flip-flops.
2. Related Art
Typically, flip-flops in IC circuits are single-edge triggered. Such flip-flops latch a state on either a positive edge transition of a clock (logical LOW, e.g., “0” to logical HIGH, e.g., “1” transition), or on a negative edge transition of the clock (“1” to “0” transition). A faster data rate and some power savings can be achieved if the state element is designed such that it latches the state on the positive as well as the negative edge of the clock. The type of flip-flop that latches on both the positive edge and negative edge of the clock is known as a dual-edge triggered flip-flop. FIG. 1 is a circuit diagram of a known single-edge triggered (SET) design 100. Shown in a series configuration starting from the left, an input passes through a control gate 102 being controlled by a complementary clock CK_B or CK 132. The output of the control gate 102 is fed to a master portion of the flip-flip or latch 104 and the output of the master latch 104 is fed to control gate 106 controlled by clock CK 136. The output of the control gate 106 is fed to a slave latch 108. The corresponding single-edge clock signals shown in FIG. 2 for single-edge trigger are 200 and 250. Note that both the SET design 100 and DET design 150 are edge sensitive devices. The data storage in these edge-sensitive flip-flops occurs at specific edges of clock signals. In the SET design 100 data is “launched” or moves forward at each rising clock edge 212 and 216.
Also shown in FIG. 1 is a known double-edge triggered (DET) design 150 including complementary clocks CKD 182 and CKD_B 188. The corresponding clock signals 250, shown in FIG. 2 for dual-edge trigger, are 262 and 268. The DET design 150 the input is fed to a de-multiplexer 152 to select between one of two parallel path master-slave 154 or slave master 156 before going into multiplexer 158.
During each clock period in the DET design 150, single-edge triggered flip-flops are triggered by, and store data at, only one edge—the rising edge 262 or the falling edge 268—of the clock signal. In the DET design 150 there are two data paths master-slave (M/S) 144 and slave-master (S/M) 142. The data flows through one of these two data paths 144, 142 depending on whether is it a rising or falling clock edge 262 or 268. More specifically, for the rising clock edge 262 data flows through M/S 154 and through S/M 156 for the falling clock edge 268.